| Tuesday, October 13 | |
| 09:00-17:30 | Workshop on Profile and Feedback-Directed Compilation |
| Workshop on Reconfigurable Computing | |
| 18:00-21:00 | Wine and Cheese Reception |
| Wednesday, October 14 | |
| 09:25-09:30 | Welcoming remarks - Ulrich Finger, ENST, France, General co-chair |
| 09:30-10:30 | Keynote Speaker: Gordon Bell, Senior Researcher, Microsoft |
| Title: What Architectures? When? || Presentation slides | |
| 10:30-10:50 | Break |
| 10:50-11:40 | Session 1: Loop transformations |
| Chair: Christine Eisenbeis, INRIA, France | |
| Scanning Polyhedra without Do-loops || Presentation slides, P. Boulet, Laboratoire d'Informatique Fondamentale de Lille, France; P. Feautrier, Université de Versailles - St Quentin, France | |
| Integrating Loop and Data Transformations for Global Optimisation, M. O'Boyle, Univ. of Edinburgh, UK; P. Knijnenburg, Leiden Univ., The Netherlands | |
| 11:40-11:55 | Break |
| 11:55-13:10 | Session 2: Shared memory design techniques |
| Chair: Nigel Topham, Univ. Edinburgh, UK | |
| Optical versus electronic bus for Address-transactions in future SMP architectures, W. Hlayhel, D. Litaize, Université Paul Sabatier Toulouse, France; L. Fesquet, J. Collet, CNRS, Toulouse, France | |
| Origin 2000 Design Enhancements for Communication Intensive Applications, G. Abandah, Univ. of Jordan; E. Davidson, Univ. of Michigan | |
| Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory, I. Schoinas, Intel; B. Falsafi, Purdue Univ.; M. Hill, J. Larus, D. Wood, Univ. of Wisconsin | |
| 13:10-14:25 | Lunch break |
| 14:25-15:30 | Session 3: Specialized multiprocessor systems |
| Chair: Hidehiko Tanaka, University of Tokyo | |
| Design Study of Shared Memory in VLIW Video Signal Processors, Z. Wu, W. Wolf, Princeton Univ. | |
| Exploiting Fine- and Coarse-grain Parallelism in Embedded Programs, I. Karkowski, H. Corporaal, Delft Univ. of Technology, The Netherlands | |
| Command Vector Memory Systems: High Performance at Low Cost, J. Corbal, R. Espasa, M. Valero, UPC-Barcelona, Spain | |
| 15:30-15:40 | break |
| 15:40-16:25 | Session 4: Parallel programming languages |
| Chair: Paraskevas Evripidou, Univ. Cyprus | |
| Eliminating Bottlenecks on Parallel Systems using Adaptive Objects, M. Yasugi, Kyoto Univ., Japan; S. Eguchi, K. Taki, Kobe Univ., Japan | |
| Athapascan-1: On-line building data flow graph in a parallel language || Presentation slides, F. Gallilée, J.L. Roch, G. Cavalheiro, M. Doreille, Lmc-Imag Apache, France | |
| General Parallel Computation Can be Performed with a Cycle-Free Heap, J. Dennis, MIT | |
| 16:25-16:40 | Break |
| 16:40-18:00 | Session 5: Short papers |
| Chair: Jack Dennis, MIT | |
| Code Generation in the Polytope Model || Presentation slides, M. Griebl, C. Lengauer, S. Wetzel, Univ. of Passau, Germany | |
| Handling Cross Interferences by Cyclic Cache Line Coloring || Presentation slides, D. Genius, Univ. of Karlsruhe, Germany | |
| Capturing the Effects of Code Improving Transformations || Presentation slides, C. Jaramillo, R. Gupta, M. Soffa, Univ. of Pittsburgh | |
| Fast, Accurate and Flexible Data Locality Analysis, J. Sanchez, A. Gonzalez, UPC - Barcelona, Spain | |
| Superscalar Execution With Direct Data Forwarding, S. Önder, R. Gupta, Univ. of Pittsburgh | |
| A Fast Interrupt Handling Scheme for VLIW Processors, E. Özer, S. Sathaye, K. Menezes, S. Banerjia, M. Jennings, T. Conte, North Carolina State Univ. | |
| Dynamic Elimination of Pointer-Expressions, N. Weinberg, D. Nagle, Carnegie Mellon Univ. | |
| Efficacy and Performance Impact of Value Prediction, B. Rychlik, J. Faistl, B. Krug, J. Shen, Carnegie Mellon Univ. | |
| 18:00-19:00 | Short paper discussion and reception |
| Thursday, October 15 | |
| 09:00-10:00 | Keynote Speaker: Carole Dulong, Principal Engineer, IA-64 Architect, Intel |
| Title: "Next Generation ILP" || Presentation slides | |
| 10:00-10:20 | Break |
| 10:20-11:10 | Session 6: ILP scheduling techniques |
| Chair: Uwe Schwiegelshohn, Univ. Dortmund, Germany | |
| A fast algorithm for scheduling time-constrainted instructions on processors with ILP, A. Leung, K. Palem, New York Univ.; A. Pnueli, The Weizmann Institute of Science, Israel | |
| A New Framework for Integrated Global Local Scheduling, S. Mantripragada, S. Jain, J. Dehnert, Silicon Graphics | |
| 11:10-11:25 | Break |
| 11:25-12:05 | Session 7: JAVA and multithreading multiprocessors |
| Chair: Jean-Luc Gaudiot, USC | |
| Exploiting Method-Level Parallelism in Single-Threaded Java Programs, M. Chen, K. Olukotun, Stanford Univ. | |
| The StarT-Voyager Parallel System, B. Ang, D. Chiou, L. Rudolph, Arvind, MIT | |
| 12:05-12:20 | Break |
| 12:20-13:10 | Session 8: Register allocation |
| Chair: Guang Gao, Univ. Delaware | |
| Optimistic Register Coalescing J. Park, S. Moon, Seoul National Univ., Korea | |
| Efficient JavaVM Just-in-Time Compilation, A. Krall, Technische Universität Wien, Austria | |
| 13:10-14:25 | Lunch break |
| 14:25-15:10 | Session 9: Branch and value prediction |
| Chair: Mateo Valero, UPC Barcelona, Spain | |
| Improving Static Branch Prediction in a Compiler, B. Deitrich, Motorola; B. Cheng, W. Hwu, Univ. of Illinois | |
| Static Methods in Hybrid Branch Prediction, D. Grunwald, D. Lindsay, B. Zorn, Univ. of Colorado | |
| Split Last-Address Predictor || Presentation slides, E. Morancho, J. Llaberia, A. Olive, Universidad Politecnica de Catalunya, Spain | |
| 15:10-15:20 | Break |
| 15:20-16:30 | Session 10: Message passing systems |
| Chair: Claude Girault, Univ. Paris VI, France | |
| Madeleine: An Efficient and Portable Communication Interface for RPC-based Multithreaded Environments || Presentation slides, L. Bougé, ENS Lyon, France; J. Méhaut, Université de Lille I, France; R. Namyst, ENS Lyon, France; | |
| Breaking the Barriers: Two Models for MPI Programming J. Roda, C. Rodriguez, D. Morales, F. Almeida, P. Pulido, D. Dorta, Universidad de la Laguna, Spain | |
| Adaptive Receiver Notification for Non-Dedicated Workstation Clusters, M. Schmitt, M. Ibel, A. Acharya, K. Schauser, Univ. of California at Santa Barbara | |
| Performance of Message-Passing Systems Using a Zero-Copy Communication Protocol P. Melas, E. Zaluska, Univ. of Southampton, UK | |
| 16:30-16:45 | Break |
| 16:45-18:15 | Panel: What should be the role of government intervention in advancing high performance computing? Views from around the world. |
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Panelists:
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| 19:00-21:30 | Conference Dinner in the Louvre |
| Friday, October 16 | |
| 09:00-10:00 | Keynote Speaker: Maurice V. Wilkes, Staff Advisor on Research Policy, Olivetti and Oracle Research Lab, Cambridge, UK |
| CMOS Workstations and Servers---How Far Can Evolution and Innovation Take Us? || Keynote speech in HTML | |
| 10:00-10:25 | Break |
| 10:25-11:40 | Session 11: ILP topics |
| Chair: Bob Rau, HP Labs | |
| Dynamic Hammock Predication for Non-predicated Instruction Set Architectures , A. Klauser, Univ. of Colorado; T. Austin, Intel; D. Grunwald, Univ. of Colorado; B. Calder, Univ. of California at San Diego | |
| A Direct-Execcution Framework for Fast and Accurate Simulation of Superscalar Processors, V. Krishnan, J. Torrellas, Univ. of Illinois | |
| Efficient Edge Profiling for ILP-Processors A. Eichenberger, S. Lobo, North Carolina State Univ. | |
| 11:40-11:55 | Break |
| 11:55-13:10 | Session 12: Cache locality improvement techniques |
| Chair: Paul Feautrier, Univ. Versailles St-Quentin, France | |
| A Matrix-Based Approach to the Global Locality Optimization Problem || Presentation slides, M. Kandemir, Syracuse Univ.; A. Choudhary, Northwestern Univ.; J. Ramanujam, Louisiana State Univ.; P. Banerjee, Northwestern Univ. | |
| Transformations for Improving Data Access Locality in Non-perfectly Nested Loops, D. Kulkarni, IBM | |
| Improving Cache Behavior of Dynamically Allocated Data Structures || Presentation slides, D. Truong, F. Bodin, A. Seznec, IRISA/INRIA, France | |
| 13:10-14:25 | Lunch break |
| 14:25-15:15 | Session 13: Data dependence and flow analysis |
| Chair: Jim Dehnert, SGI | |
| Instance-wise Reaching Definition Analysis for Recursive Programs Using Context-free Transductions || Presentation slides, A. Cohen, J. Collard, Université de Versailles, France | |
| Data Dependence Analysis of Assembly Code, W. Amme, P. Braun, Univ. of Jena, Germany; F. Thomasset, INRIA, Rocquencourt, France; E. Zehendner, Univ. of Jena, Germany | |
| 15:15-15:25 | Break |
| 15:25-16:20 | Session 14: Task scheduling and dynamic load balancing |
| Chair: Michel Cosnard, Loria, France | |
| Load Balancing in Individual-Based Spatial Applications, M. Dillencourt, L. Bic, F. Merchant, UC Irvine | |
| A New Heuristic for Scheduling Parallel Programs on Multiprocessor, J. Liou, AT&T Laboratories; M. Palis, Rutgers Univ. | |
| Adaptive Scheduling of Computations and Communications on Distributed Memory Systems, M. Al-Mouhamed, H. Najjari, King Fahd Univ., Saudi Arabia | |
| 16:20-16:35 | Break |
| 16:35-17:35 | Session 15: Topics in compilation |
| Chair: Christian Lengauer, Univ. Passau, Germany | |
| Using Algebraic Transformations to Optimize Expression Evaluation in Scientific Code, J. Zory, F. Coelho, École des Mines de Paris, France | |
| Integrated Compilation and Scalability Analysis for Parallel Systems || Presentation slides, C. Mendes, National Institute of Space Research, Brazil; D. Reed, Univ. of Illinois | |
| Improving Compiler and Run-Time Support for Adaptive Irregular Codes, H. Han, C. Tseng, Univ. of Maryland | |
| On the parallelization of Benchmarks for SSM Machines Y. Paek, New Jersey Institute of Technology; A. Navarro, E. Zapata, Univ. of Malaga, Spain; D. Padua, Univ. of Illinois | |
| 17:35-17:50 | Break |
| 17:50-18:35 | Session 16: Compilation for distributed memory |
| Chair: Makoto Amamiya, Kyushu Univ., Japan | |
| Efficient Methods for Multi-Dimensional Array Redistribution Y. Chung, C. Hsu, Feng Chia Univ., R.O.C. | |
| A multithreaded runtime environment with thread migration for a HPF data-parallel compiler || Presentation slides, L. Bougé, ENS Lyon, France; P. Hatcher, Univ. New Hampshire; R. Namyst, C. Perez, ENS Lyon, France | |
| Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR, S. Goto, Sumitomo Electric Industries,Ltd.; A. Kubota, Hiroshima City Univ.; T. Tanaka, M. Goshima, S. Mori, Kyoto Univ., Japan; H. Nakashima, Toyohashi Univ. of Tenology; S. Tomita, Kyoto Univ., Japan | |
| 18:35-18:40 | Best paper award presentations, and closing remarks |
| Saturday, October 17: Tutorials | |
| 09:00-12:00 | Trimaran Compiler Infrastructure, B. Goldberg, H. Kim, K. Palem, NYU; B. Rau, HP Labs |
| 14:00-17:00 | The Tera Multithreaded Architecture, J. Feo, P. Briggs, Tera |
| Monday, October 19 | |
| 09:00-17:00 | Workshop on Tera Programming |