The TERA Multithreaded Architecture

Preston Briggs and John Feo

Tera Computer

The TERA MTA is a highly-integrated multithreaded architecture. It is a scalable, shared memory MIMD computer system that can execute efficiently coarse-, medium- and fine-grain parallelism. Unlike other commercial MPP and SMP systems, the MTA has no local memory and no caches. Each processor is 128 virtual processors feeding a single instruction pipeline. As long as one virtual processor can issue an instruction every cycle, the processor remains fully utilized. Performance is limited only by parallelism; data locality, granularity, and task scheduling for load balancing are non-issues.

The MTA is a highly-integrated system. The goal of the hardware architects is to build a scalable, high-performance computer that simplifies compilation and parallel application development. The same is true of the software engineers developing the system's operating system, compilers, and tools. Many design decision are heavily influenced by this objective.

In this tutorial, we will describe the MTA's architecture, operating system, and programming model in detail. We will define the terms memory latency, memory bandwidth, and concurrency, and show how the three are related. We will give a detail description of the processor, network, and memory system, explaining how features in each simplify compilation and program development. We will describe the dynamic and highly parallel nature of the operating system, and show how it supports program execution and debugging. Finally, we will present the programming model (loop parallelism, future statements, fine-grain synchronization) and point out some of the unique features of TERA's software tools.

Breakdown

20% beginner
50% intermediate
30% advance

About the Speakers

Preston Briggs leads the compiler group at Tera Computer and assists with benchmarking, application tuning, documentation, user training, etc. Before coming to Tera, he was a research scientist at Rice, working on the Massively Scalar Compiler project. He has a PhD from Rice.

John Feo is a staff scientist at Tera Computer Company. He is the company's site representative at the San Diego Supercomputer Center. Before joining Tera he was the Group Leader for the Computer Research Group at Lawrence Livermore National Laboratory and principal investigator of the Sisal Language Project. He is a lecturer in the Computer Science Department at UC, Davis. His areas of interest are parallel programming, scientific applications, programming languages, and performance.

Back to PACT'98 homepage