Multithreaded Computer Architecture
Jack B. Dennis, M.I.T. Laboratory for Computer Science
Monday, June 26, 1995
Abstract
Multithreaded computer architecture is emerging as an
important alternative to building multiprocessor computers
using standard RISC or superscalar processor chips.
Multithreaded architecture combines the ability of
conventional processors to achieve fast execution
of sequential code with support for quickly switching
among threads of control to tolerate memory access
latency and to avoid wasteful delays for synchronization.
We will concentrate on three approaches to multithreaded
architecture: A commercial venture -- the Tera MTA; a novel
research multiprocessor -- the MIT Monsoon Project; and the
efforts in several laboratories to implement efficient multithreaded
computing through software layers on and hardware extensions
of off-the-shelf commodity microprocessors.
Topics considered will include:
- What is a thread?
- Blocking versus non-blocking threads
- Mechansisms for implmenting threads
- How do you generate threaded code?
- Interleaved versus conventional pipeline design
- Cache-coherence in multithreaded architecture
- Processor interconnection networks and multithreaded architecture
- Program execution models for multithreaded architecture
- Application areas that can benefit from multithreading
- Prospects for future development
Brief biography:
Jack Dennis is widely known for his contributions to computer
architecture including memory organization to support paging
and segmentation, and multiprocessor computer architecture
guided by dataflow concepts. He has developed and taught many
subjects in the fields of electrical engineering and computer
science, has guided the research of more than 25 doctoral
research students, and is a valued consultant to industry.
Dr. Dennis is the recipient of the 1984 Eckert/Mauchly Award
for contributions to computer architecture, and is a Fellow of
the IEEE and of the ACM.