Mechanisms for exploiting instruction-level parallelism
Yale Patt, University of Michigan.
Monday, June 26
Course Outline
- Introduction and Focus (5%)
- What are we after
- What can the compiler bring to the table
- What can the microarchitecture bring to the table
- Recent Experiments (5%)
- "Yeh's Algorithm," the Intel P-6 Branch Predictor
- Choice of Scheduling mechanism
- State Maintenance (SGI adopts checkpointing)
- Multiple branches per cycle
- What is going on today (5%)
- Our Key Thrusts for 1995
- After Yeh's Algorithm, what?
- Block-structured ISA
- The VLIW Hiccup
- What else is important
The topics:
- The critical problems (introduction, focus, and overview)
- A symbiosis of the compiler and the microarchitecture
- Where VLIW fits in (if it does)
- Instruction supply -- branch prediction ("Yeh's Algorithm" on Intel's P-6,
and what we have been doing at Michigan since Yeh graduated!)
- Instruction execution
- Instruction retirement
- What can the compiler provide (Static tags, block atomic units, etc.)
- What the marketplace has recently introduced
(the souls of some new machines).
- My expectations for the near-term future.
Brief biography:
Yale Patt teaches undergraduate and graduate courses in computer architecture
and directs nine PhD students in research relating to high performance
computer implementation at the University of Michigan, Ann Arbor. In addition,
he has been teaching short courses on computer architecture and implementation
to practicing engineers in the computer industry continually since 1983. He
has been an active consultant to industry on both microprocessor design
projects, and systems integration projects for more than 25 years, notably to
AT&T GIS (since 1986) and to DEC (since 1977). Dr. Patt studied electrical
engineering at Northeastern University (BS) and Stanford University (MS, PhD).
He is a Fellow of the IEEE. Dr. Patt is the 1995 recipient of the IEEE
Emmanuel R. Piore Award "for contributions to computer architecture leading
to commercially viable high performance microprocessors."